1. Field of the Invention
This invention relates to the field of computer hardware design verification, specifically in the area of cycle simulation. Disclosed herein is a method for constructing a Hybrid Cycle Simulation model comprised of a mixture of Compiled Data Units (CDUs). Said simulation model may contain a plurality of 1-cycle CDUs, optimized for simulation throughput, and 2-cycle CDUs, optimized for simulation accuracy. Additionally, the present invention contemplates a software entity FACDDR which implements a method to permit high bandwidth simulation of design components normally requiring cycle accurate simulation.
2. Description of Background
There have been many improvements in the area of hardware design verification and cycle simulation necessitated by the ever increasing complexity of integrated circuit designs at IBM. This increased complexity translates to substantial development and manufacturing expense, which is directly proportional to the number of design fabrication iterations. One approach to controlling these costs is to perform robust verification through cycle simulation. Prior to our invention, there existed the use of cycle simulation where the evaluation is only performed on the clock boundaries instead of every unit of clock time. The advantage of cycle simulation is the tremendous performance boost compared to traditional event based simulation. The cycle simulation models can be modeled in 2 different ways. These are commonly referred to as a single cycle simulation model (hereafter referred to as 1-cycle simulation) or a two-cycle (2-cycle) simulation model.
A single cycle simulation model makes a single evaluation of the latches per machine cycle. This results in a faster simulation because the latches are only evaluated at the L2 boundary. The L1 latches are treated as wires. Since simulation performance is also directly related to model size, it is often desirable to eliminate portions of the design that can't benefit from single cycle simulation. For example, functions like clocking, phased lock loops and Built-In Self Test (BIST) can rarely be effectively validated in a 1-cycle simulation environment. Instead, the single cycle simulation model is used for the majority of main line function because it is sufficient for testing typical machine operations.
The benefits of single cycle simulation include smaller model size and faster simulation throughput. Smaller model size is particularly important on hardware simulators with limited capacity and resulting in smaller event traces for problem debug. Faster throughput allows for flushing through problems faster using fewer workstations to produce the same number of simulation clocks. The disadvantage is that behavioral “black boxes” are required to represent some parts of the design, such as the aforementioned functions.
A two cycle simulation model makes two simulation evaluations of the latches per machine cycle. The latches are divided into L1 and L2 latches such that the L1 latches are evaluated on the rising edge of the global system clock and the L2 latches are evaluated on the falling edge of the global system clock. This allows for the modeling of certain test functions such as machine initialization via scanning. One major advantage of the 2-cycle model is the modeling of pervasive functions like clocking, scanning, I/O, array verification, firmware validation and BIST logic. While significantly faster than an event simulation, the 2-cycle simulation has slower performance than a 1-cycle simulation and is larger in size. Additional information on the advantages of cycle simulation and the differences between 1-cycle and 2-cycle simulation can be found in the IBM Journal of Research and Development Volume 41, Number 4/5, dated July/September 1.
Although many inventions in the related art field solve many of the problems and shortcomings faced by hardware designers, they fail to address several aspects of the present invention. For example:                U.S. Pat. No. 6,240,376 entitled Method and Apparatus for Gate Level Simulation of Synthesized Register Transfer Level Designs with Source Level Debugging, issued to Raymond et al., provides a method to cross reference a gate level netlist with register transfer language source for purposes of interactive debug and source code simulation coverage.        U.S. Pat. No. 5,696,942 entitled Cycle Based Event Driven Simulator for Hardware Designs, issued to Palnitkar et al., describes a means of efficiently ordering and evaluating logic transitional events in a cycle simulation environment.        U.S. Pat. No. 6,604,065 entitled Multiple State Simulation for Non-Binary Logic, issued to Blomgren et al. teaches a method for efficiently simulating hardware designs that entail the use of non-binary logic levels.        U.S. Pat. No. 6,842,728 entitled Time Multiplexing Data Between Asynchronous Clock Domains Within Cycle Simulation and Emulation Environments, issued to Gooding et al., illustrates an apparatus which permits a hardware design comprised of a plurality of different frequency domains to efficiently transfer signals between them in a hardware emulator.        U.S. Pat. No. 6,625,572 entitled Cycle Modeling in Cycle Accurate Software Simulators of Hardware Modules for Software/Software Cross Simulation and Hardware/Software Co-simulation, issued to Zemlyak et al., provides a method of modeling a processor in a cycle simulation environment through the use of software to permit co-simulation between a multitude of software and hardware entities.        Finally, U.S. Pat. No. 6,523,155 entitled Method for Partitioning a Netlist into Multiple Clock Domains, issued to Ruedinger, describes a means of automatically partitioning a hardware design netlist comprised of a plurality of clock domains, into multiple domains for purposes of parallel cycle or event based simulation.        
While the aforementioned inventions are considered innovative in the area of hardware design verification, none of them, either individually, or taken in combination, address the need to balance simulation performance throughput against behavioral accuracy in a cycle simulation environment. However, one skilled in the art may appreciate how several of the prior art inventions would complement, and incorporate into, our invention.